1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a manufacturing method thereof, and more particularly, it relates to the structure of a flash memory and a manufacturing method thereof.
2. Description of the Related Art
Nonvolatile semiconductor memories such as flash memories are installed in various electronic devices as storage devices.
Flash memories are required to have increased storage capacities, and are being reduced in element size. Recently, there has been proposed, for example, a sidewall fabrication technique to obtain a dimension smaller than a fabrication limit dimension of lithography (exposure) (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2006-156657).
Storage capacity is also increased by elaborately designing the layout and structure of interconnect lines in the flash memory. One such example is the shape of a contact for connecting a memory cell or a memory cell unit including a plurality of memory cells to a source line. In the flash memory, taking its operation into account, the source line connected to the memory cell (memory cell unit) can be shared because the source line is collectively controlled by the plurality of memory cells arranged in the extending direction of the source line. Thus, a linear contact that can be shared by the plurality of memory cells is used in the flash memory. The use of such a linear (referred to as an LI structure) contact makes it possible to reduce the dimensions of the contact.
When the above-mentioned sidewall fabrication technique is used to form an active area in a memory cell array, the memory cell array has a structure in which the active areas and element isolation areas (isolation insulating films) are alternately arranged in the extending direction of the contact of the LI structure. In this case, the bottom of the contact of the LI structure is in contact with the active areas and the isolation insulating films.
When a linear trench is formed to embed the contact in an interlayer insulating film located on the active area and the isolation insulating film in order to form the contact of the LI structure, the upper surface of the active area and the upper surface of the isolation insulating film are subjected to an etching condition for the interlayer insulating film. Here, it is often the case that, with respect to the etching condition for the interlayer insulating film, a sufficient degree of etching selectivity cannot be ensured for the isolation insulating film in contrast with the active area. As a result, the isolation insulating film is etched, and the upper end of the isolation insulating film drops toward a semiconductor substrate further than the upper end of the active area.
Consequently, the surface of the semiconductor substrate in a contact area is unevenly structured, and the bottom of the contact of the LI structure is structured to be in contact with not only the upper surface of the active area but also the side surface of the active area.
Accordingly, the dielectric breakdown voltage of the isolation insulating film decreases, which causes deterioration of element characteristics such as an increased leakage current.